HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 139

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

4.4
4.4.1
The reset sequence is used to power up or restart the SH7709S from the initialization state. The
RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset,
all processing being executed (excluding the RTC) is suspended, all unfinished events are
canceled, and reset processing is executed immediately. In the case of a manual reset, however,
reset processing is executed after completion of any memory access being executed. The reset
sequence consists of the following operations:
1. The MD bit in SR is set to 1 to place the SH7709S in privileged mode.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt
3. The RB bit in SR is set to 1.
4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11–
5. Instruction execution jumps to the user-written exception handler at address H'A0000000.
4.4.2
An interrupt handling request is accepted on completion of the current instruction. The interrupt
acceptance sequence consists of the following operations:
1. The contents of PC and SR are saved to SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt
3. The MD bit in SR is set to 1 to place the SH7709S in privileged mode.
4. The RB bit in SR is set to 1.
5. An encoded value identifying the exception event is written to bits 11–0 of the INTEVT and
6. Instruction execution jumps to the vector location designated by the sum of the value of the
when the BLMSK bit is 1).
0 of the EXPEVT register to identify the exception event.
when the BLMSK bit is 1).
INTEVT2 registers.
contents of the vector base register (VBR) and H'00000600 to invoke the exception handler.
Exception Handling Operation
Reset
Interrupts
Rev. 5.00, 09/03, page 93 of 760