HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 108

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5. The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the
The MMU registers are shown in figure 3.3.
Rev. 5.00, 09/03, page 62 of 760
MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in
the P1 or P2 area.
RC: A 2-bit random counter, automatically updated by hardware according to the
SV: Single virtual memory mode bit.
Note: * Refer to section 3.3, TLB Functions.
AT: Address translation bit. Enables/disables the MMU.
TF: TLB flush bit. Write 1 to flush the TLB (clear all valid bits of the TLB to 0). Always
IX: Index mode bit. When 0, VPN bits 16−12 are used as the TLB index number.
0: Reserved bits. Always read as 0. Writing is ignored. However, 0 should also be
specified in a write to MMUCR only.
following rules in the event of an MMU exception. When a TLB miss exception
occurs, all TLB entry ways corresponding to the virtual address at which the
exception occurred are checked, and if all ways are valid, 1 is added to RC; if
there is one or more invalid way, they are set by priority from way 0, in the order:
way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB
miss exception, the way which caused the exception is set in RC.
reads 0.
When 1, the value obtained by EX-ORing ASID bits 4−0 in PTEH and VPN bits
16−12 are used as the TLB index number.
0: MMU disabled
1: MMU enabled
31
31 29 28
31
31
31
000
Figure 3.3 MMU Register Contents
Virtual address causing TLB-related
PPN
or address error exception
0
VPN
MMUCR
PTEH
PTEL
TTB
TTB
TEA
0: Multiple virtual memory mode
1: Single virtual memory mode
10
10
0
9
8
V
SV
8
*
0
7
0
7
00
PR
6
7
6 5
*
RC
SZ
4 3 2 1 0
4
ASID
*
3 2 1
0 TF IX AT
C
*
D
*
SH
*
0
0
0
0
0