HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 512

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 14.11.
Clock: See the description in the asynchronous mode section.
Transmitting Multiprocessor Serial Data: Figure 14.13 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data
is:
1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that
2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if
3. To output a break at the end of serial transmission: Set the port SC data register (SCPDR) and
Rev. 5.00, 09/03, page 466 of 760
Serial
the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR). Also set
MPBT (multiprocessor bit transfer) to 0 or 1 in SCSSR. Finally, clear TDRE to 0.
it reads 1); if so, write data in SCTDR, then clear TDRE to 0.
port SC control register (SCPCR), then clear the TE bit to 0 in the serial control register
(SCSCR). For SCPCR and SCPDR settings, see section 14.2.8, SC Port Control Register
(SCPCR)/SC Port Data Register (SCPDR).
data
MPB: Multiprocessor bit
Figure 14.12 Communication Among Processors Using Multiprocessor Format
Transmitting
Receiving
station A
(ID = 01)
station
specifies receiving station
(Sending Data H'AA to Receiving Processor A)
ID transmit cycle:
H'01
Receiving
(MPB = 1)
station B
(ID = 02)
Serial communication line
receiving station specified
data transmission to
Data transmit cycle:
Receiving
station C
(ID = 03)
H'AA
by ID
(MPB = 0)
Receiving
(ID = 04)
station D