HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 105

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Physical Address Space: The SH7709S supports a 32-bit physical address space, but the upper 3
bits are actually ignored and treated as a shadow. See section 10, Bus State Controller (BSC), for
details.
Address Translation: When the MMU is enabled, the virtual address space is divided into units
called pages. Physical addresses are translated in page units. Address translation tables in external
memory hold information such as the physical address that corresponds to the virtual address and
memory protection codes. When an access to an area other than P4 occurs, if the accessed virtual
address belongs to area P1 or P2 there is no TLB access and the physical address is uniquely
defined. If it belongs to area P0, P3, or U0, the TLB is searched by virtual address and, if that
virtual address is registered in the TLB, the access hits the TLB. The corresponding physical
address and the page control information are read from the TLB and the physical address is
determined.
H'80000000
H'A0000000
H'C0000000
H'E0000000
H'FFFFFFFF
H'00000000
(write-back/write-through)
(write-back/write-through)
(write-back/write-through)
0.5-Gbyte fixed physical
0.5-Gbyte control space,
0.5-Gbyte virtual space,
2-Gbyte virtual space,
space, cacheable
0.5-Gbyte fixed
Privileged mode
physical space,
non-cacheable
non-cacheable
cacheable
cacheable
Figure 3.2 Virtual Address Space Mapping
Area P0
Area P1
Area P2
Area P3
Area P4
H'00000000
H'80000000
H'FFFFFFFF
(write-back/write-through)
2-Gbyte virtual space,
Rev. 5.00, 09/03, page 59 of 760
Address error
User mode
cacheable
Area U0