HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 284

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 6: A6BST1
0
1
Bits 4 to 2—Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): Designate
the types of memory connected to physical space areas 2 and 3. Ordinary memory, such as ROM,
SRAM, or flash ROM, can be directly connected. Synchronous DRAM can also be directly
connected.
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
1
Notes: 1. When selecting this mode, set the same bus width for area 2 and area 3.
Bit 1—Area 5 Bus Type (A5PCM): Designates whether to access physical space area 5 as
PCMCIA space.
Bit 1: A5PCM
0
1
Rev. 5.00, 09/03, page 238 of 760
2. Do not access synchronous DRAM when clock ratio I :B = 1:1
0
1
0
1
Bit 5: A6BST0
0
1
0
1
Description
Physical space area 5 accessed as ordinary memory
Physical space area 5 accessed as PCMCIA space
0
1
0
1
0
1
0
1
Description
Access area 6 accessed as ordinary memory
Burst access of area 6 (4 consecutive accesses). Can
be used when bus width is 8, 16, or 32.
Burst access of area 6 (8 consecutive accesses). Can
be used when bus width is 8 or 16. Should not be
specified when bus width is 32.
Burst access of area 6 (16 consecutive accesses). Can
be used only when bus width is 8. Should not be
specified when bus width is 16 or 32.
Areas 2 and 3 are ordinary memory
Reserved (Setting prohibited)
Area 2: ordinary memory; area 3:
synchronous DRAM *
Areas 2 and 3 are synchronous DRAM *
*
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Reserved (Setting prohibited)
2
2
(initial value)
(Initial value)
(Initial value)
1