HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 542

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

15.3.3
Figure 15.3 shows the data format for the smart card interface. In this mode, parity is checked
every frame while receiving and error signals sent to the transmitting side whenever an error is
detected so that data can be re-transmitted. During transmission, error signals are sampled and data
re-transmitted whenever an error signal is detected.
The operating sequence is:
1. The data line is high-impedance when not in use and is fixed high with a pull-up register.
2. The transmitting side starts one frame of data transmission. The data frame starts with a start
3. On the smart card interface, the data line returns to high-impedance after this. The data line is
4. The receiving side checks parity. When the data is received normally with no parity errors, the
Rev. 5.00, 09/03, page 496 of 760
bit (Ds, low level). The start bit is followed by eight data bits (D0–D7) and a parity bit (Dp).
pulled high with a pull-up register.
receiving side then waits to receive the next data. When a parity error occurs, the receiving
side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving
station returns the signal line to high-impedance after outputting the error signal for a specified
period. The signal line is pulled high with a pull-up register.
D0−D7:
With no parity error
With parity error
DE:
Dp:
Ds:
Data Format
Ds
Ds
Start bit
Data bits
Parity bit
Error signal
D0
D0
Figure 15.3 Data Format for Smart Card Interface
D1
D1
Transmitting station output
Transmitting station output
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Dp
Dp
station output
Receiving
DE