HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 570

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from the
transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data
in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and
TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is
enabled.
Bit 5: TDFE
0
1
Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be
Bit 4—Break Detection (BRK): Indicates that a break signal has been detected in receive data.
Bit 4: BRK
0
1
Note: * When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after
Rev. 5.00, 09/03, page 524 of 760
written when TDFE is 1 is “16 minus the specified transmission trigger number”. If an
attempt is made to write additional data, the data is ignored. The quantity of data in
SCFTDR is indicated by the upper 8 bits of SCFTDR.
detection. When the break ends and the receive signal becomes mark 1, the transfer of
receive data resumes. The receive data of a frame in which a break signal is detected is
transferred to SCFRDR. After this, however, no receive data is transferred until a break
ends with the received signal being mark 1, and the next data is received.
Description
The quantity of transmit data written to SCFTDR is greater than the specified
transmission trigger number
[Clearing condition]
TDFE is cleared to 0 when data exceeding the specified transmission trigger
number is written to SCFTDR, or when software reads TDFE after it has been
set to 1, then writes 0 to TDFE
The quantity of transmit data in SCFTDR is less than the specified transmission
trigger number *
[Setting conditions]
(1) TDFE is set to 1 by a reset or in standby mode
(2) When the quantity of transmit data in SCFTDR becomes less than the
Description
No break signal received
[Clearing conditions]
(1) BRK is cleared to 0 when the chip is reset or enters standby mode
(2) When software reads BRK after it has been set to 1, then writes 0 to BRK
Break signal received *
[Setting conditions]
(1) BRK is set to 1 when data including a framing error is received
(2) A framing error occurs with space 0 in the subsequent receive data
specified transmission trigger number as a result of transmission
(Initial value)
(Initial value)