HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 585

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected
by bits CKE1 and CKE0 in the serial control register (SCSCR) (table 16.8).
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCIF operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is 16 times the bit rate.
Transmitting and Receiving Data (SCIF Initialization): Before transmitting or receiving, clear
the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows.
When changing the communication format, always clear the TE and RE bits to 0 before following
the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR).
Clearing TE and RE to 0, however, does not initialize the serial status register (SCSSR), transmit
FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their
previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in
the SCSSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to
the high impedance state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset
SCFTDR before TE is set again to start transmission.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCIF operation becomes unreliable if the clock is stopped.
Figure 16.5 shows a sample flowchart for initializing the SCIF. The procedure for initializing the
SCIF is:
1. Set the clock selection in SCSCR.
2. Set the communication format in SCSMR.
3. Write a value corresponding to the bit rate into the bit rate register (SCBRR).
4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE
Be sure to clear bits RIE TIE, TE, and RE to 0.
When clock output is selected, the clock is output immediately after SCSCR settings are made.
(Not necessary if an external clock is used.)
and TIE bits.
Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the
SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start
bit.
Rev. 5.00, 09/03, page 539 of 760