HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 484

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5: TE
0
1
Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SCSSR) is
Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 4: RE
0
1
Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit
(MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is
ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
0
1
Note: * The SCI does not transfer receive data from SCRSR to SCRDR, does not detect receive
Rev. 5.00, 09/03, page 438 of 760
2. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial
2. Serial reception starts when a start bit is detected in asynchronous mode, or
errors, and does not set the RDRF, FER, and ORER flags in the serial status register
(SCSSR). When it receives data that includes MPB
and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE
and RIE bits in the SCSCR are set to 1), and allows the FER and ORER bits to be set.
fixed at 1.
status register (SCSSR) is cleared to 0 after writing of transmit data into the SCTDR.
Select the transmit format in SCSMR before setting TE to 1.
flags retain their previous values.
synchronous clock input is detected in synchronous mode. Select the receive format in
SCSMR before setting RE to 1.
Description
Transmitter disabled *
Transmitter enabled *
Description
Receiver disabled *
Receiver enabled *
Description
Multiprocessor interrupts are disabled (normal receive operation)
[Clearing conditions]
(1) MPE is cleared to 0 when MPIE is cleared to 0.
(2) The multiprocessor bit (MPB) is set to 1 in receive data.
Multiprocessor interrupts are enabled *
Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI),
and setting of the RDRF, FER, and ORER status flags in the serial status register
(SCSSR) are disabled until data with a multiprocessor bit of 1 is received.
2
1
2
1
1, the SCSSR’s MPB flag is set to 1,
(Initial value)
(Initial value)
(Initial value)