HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 433

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11.6
1. The DMA channel control registers (CHCR0–CHCR3) can be accessed with any data size. The
2. Before rewriting the RS0–RS3 bits in CHCR0–CHCR3, first clear the DE bit to 0 (when
3. Even if an NMI interrupt is input when the DMAC is not operating, the NMIF bit in DMAOR
4. Before entering standby mode, the DME bit in DMAOR must be cleared to 0 and the transfers
5. The on-chip peripherals which the DMAC can access are the IrDA, SCIF, A/D converter, D/A
6. When starting up the DMAC, set CHCR or DMAOR last. Normal operation is not guaranteed
7. Even if the maximum number of transfers are performed in the same channel after the
8. When using the address reload function, specify burst mode as the transfer mode. In cycle-steal
9. When using the address reload function, set a multiple of four in DMATCR. Normal operation
10. When detecting an external request at the falling edge, keep the external request pin high when
11. Do not access the space from H'4000062 to H'400006F, which is not used in the DMAC.
12. The WAIT signal is ignored in the case of a write to external address space in dual address
13. DMAC transfers should not be performed in the sleep mode under conditions other than when
14. When the following three conditions are all met, the frequency control register (FRQCR)
DMA operation register (DMAOR) must be accessed by byte (8 bits) or word (16 bits); other
registers must be accessed by word (16 bits) or longword (32 bits).
rewriting CHCR with a byte address, be sure to set the DE bit to 0 in advance).
will be set.
accepted by the DMAC completed.
converter, and I/O ports. Do not access other peripherals with the DMAC.
if settings for another register are made last.
DMATCR count reaches 0 and DMA transfer ends normally, write 0 to DMATCR.
Otherwise, normal DMA transfer may not be performed.
mode, normal DMA transfer may not be performed.
is not guaranteed if other values are specified.
setting the DMAC.
Accessing this space may cause malfunctions.
mode with 16-byte transfer, or transfer from an external device with DACK to external address
space in signal address mode with 16-byte transfer.
the clock ratio of I (on-chip clock) to B (bus clock) is 1:1.
should not be changed while a DMAC transfer is in progress.
Bits IFC2 to IFC0 are changed.
STC2 to STC0 in FRQCR are not changed.
The clock ratio of I (on-chip clock) to B (bus clock) after the change is other than 1:1.
Usage Notes
Rev. 5.00, 09/03, page 387 of 760