HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 689

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table 22.1 shows the UDI register configuration.
Table 22.1 UDI Registers
Name
Bypass register
Instruction register
Boundary register
Note: * Initialized when TRST pin is low or when TAP is in the test-logic-reset state.
22.3.1
The bypass register is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the
bypass mode, SDBPR is connected between UDI pins TDI and TDO.
22.3.2
The instruction register (SDIR) is a 16-bit read-only register. The register is in bypass mode in its
initial state. It is initialized by TRST assertion or in the TAP test-logic-reset state, and can be
written to by the UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved
command is set in this register
Bits 15 to 12—Test Instruction Bits (TI3 to TI0): Cannot be written by the CPU.
Initial value:
Initial value:
Bypass Register (SDBPR)
Instruction Register (SDIR)
Bit:
Bit:
Abbreviation
SDBPR
SDIR
SDBSR
TI3
15
—
1
7
1
TI2
14
—
1
6
1
R/W
—
R
—
TI1
13
—
1
5
1
Size
—
16
—
CPU Side
TI0
12
—
1
4
1
Address
—
H'04000200
—
11
—
—
1
3
1
Rev. 5.00, 09/03, page 643 of 760
R/W
R/W
R/W
R/W
UDI Side
10
—
—
1
2
1
Size
1
16
—
—
—
9
1
1
1
Initial
Value *
Undefined
H'FFFF
Undefined
—
—
8
1
0
1