HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 451

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

12.4.2
The status flag can be cleared by writing 0 from the CPU. Figure 12.9 shows the timing.
12.4.3
The TMU produces underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, an interrupt is requested. Codes are set in the interrupt event
registers (INTEVT, INTEVT2) for these interrupts and interrupt handling occurs according to the
codes.
The relative priorities of channels can be changed using the interrupt controller (see section 4,
Exception Handling, and section 6, Interrupt Controller (INTC)). Table 12.3 lists TMU interrupt
sources.
Table 12.3 TMU Interrupt Sources
Channel
0
1
2
2
Peripheral address bus
Status Flag Clearing Timing
Interrupt Sources and Priorities
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
UNF, ICPF
P
Figure 12.9 Status Flag Clearing Timing
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2
T
1
TCR write cycle
T
2
Rev. 5.00, 09/03, page 405 of 760
TCR address
Priority
High
Low
T
3