HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 163

IC SUPERH MPU ROMLESS 208LQFP

HD6417709SF133B

Manufacturer Part Number
HD6417709SF133B
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417709SF133B

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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6.1
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
6.1.1
The INTC has the following features:
16 levels of interrupt priority can be set: By setting the five interrupt-priority registers, the
priorities of on-chip peripheral module, IRQ, and PINT interrupts can be selected from 16
levels for individual request sources.
NMI noise canceler function: An NMI input-level bit indicates the NMI pin state. By reading
this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be
used as a noise canceler.
External devices can be notified that an interrupt has been received (IRQOUT): When the
SH7709S has released the bus, the external bus master can be notified that an external
interrupt, an on-chip peripheral module interrupt, or a memory refresh request has occurred,
enabling the bus to be requested.
Overview
Features
Section 6 Interrupt Controller (INTC)
Rev. 5.00, 09/03, page 117 of 760

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