HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 424

IC SUPERH MPU ROMLESS 208LQFP

HD6417709SF133B

Manufacturer Part Number
HD6417709SF133B
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417709SF133B

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Bit 0—Count Start 0 (STR0): Selects whether to operate or halt CMCNT0.
Bit 0: STR0
0
1
Compare Match Timer Control/Status Register 0 (CMCSR0)
The compare match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the
clock used for incrementation. It is initialized to H'0000 by a reset, but retains its previous value in
standby mode.
Note: * The only value that can be written is 0 to clear the flag.
Bits 15 to 8 and 5 to 2—Reserved: These bits are always read as 0. The write value should
always be 0.
Bit 7—Compare Match Flag (CMF): Indicates whether or not the compare match timer counter
0 (CMCNT0) and compare match timer constant 0 (CMCOR0) values match.
Bit 7: CMF
0
1
Rev. 5.00, 09/03, page 378 of 760
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
R/(W) *
CMF
15
R
0
7
0
Description
CMCNT0 count operation halted
CMCNT0 count operation
Description
CMCNT0 and CMCOR0 values do not match
Clearing condition: Write 0 to CMF after reading CMF = 1
CMCNT0 and CMCOR0 values match
R/W
14
R
0
6
0
13
R
R
0
5
0
12
R
R
0
4
0
11
R
R
0
3
0
10
R
R
0
2
0
CKS1
R/W
R
9
0
1
0
(Initial value)
(Initial value)
CKS0
R/W
R
8
0
0
0

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