HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 391

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11.3
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip
module request. The dual address mode has direct address transfer mode and indirect address
transfer mode. Burst mode or cycle-steal mode can be selected as the bus mode.
11.3.1
After the DMA source address register (SAR), DMA destination address register (DAR), DMA
transfer count register (DMATCR), DMA channel control register (CHCR), and DMA operation
register (DMAOR) are set, the DMAC transfers data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of
3. When the specified number of transfers have been completed (when DMATCR reaches 0), the
4. When an address error occurs by the DMAC or an NMI interrupt is generated, the transfer is
Figure 11.2 is a flowchart of this procedure.
data (according to the TS0 and TS1 settings). For an auto-request, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented for each transfer. The actual transfer flows vary by address mode and bus mode.
transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to
the CPU.
aborted.
Operation
DMA Transfer Flow
Rev. 5.00, 09/03, page 345 of 760