HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 591

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

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Figures 16.9 and 16.10 show a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCSSR to
2. SCIF status check and receive data read : Read the serial status register (SCSSR) and check
3. Serial reception continuation procedure: To continue serial reception, read at least the receive
Serial data reception
identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK
flags to 0. In the case of a framing error, a break can also be detected by reading the value of
the RxD pin.
that RDF = 1, then read the receive data in the receive FIFO data register (SCFRDR), read 1
from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to
1 can be identified by an RXI interrupt.
trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear
the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by
reading the lower bits of SCFDR.
Rev. 5.00, 09/03, page 545 of 760