HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 486

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

14.2.7
The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and
status flags that indicate the SCI operating state.
The CPU can always read and write to SCSSR, but cannot write 1 to the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
SCSSR is initialized to H'84 by a reset and in standby or module standby mode.
Note: * The only value that can be written is 0 to clear the flag.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from SCTDR into SCTSR and new serial transmit data can be written in SCTDR.
Bit 7: TDRE
0
1
Rev. 5.00, 09/03, page 440 of 760
Initial value:
Serial Status Register (SCSSR)
R/W:
Bit:
Description
SCTDR contains valid transmit data
[Clearing condition]
TDRE is cleared to 0 when software reads TDRE after it has been set to 1.
SCTDR does not contain valid transmit data
[Setting conditions]
(1) TDRE is set to 1 when the chip is reset or enters standby mode.
(2) The TE bit in the serial control register (SCSCR) is cleared to 0.
(3) SCTDR contents are loaded into SCTSR, so new data can be written in
R/(W) *
SCTDR.
TDRE
7
1
R/(W) *
RDRF
6
0
R/(W) *
ORER
5
0
R/(W) *
FER
4
0
R/(W) *
PER
3
0
TEND
R
2
1
MPB
R
1
0
(Initial value)
MPBT
R/W
0
0