HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 256

IC SUPERH MPU ROMLESS 208LQFP

HD6417709SF133B

Manufacturer Part Number
HD6417709SF133B
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417709SF133B

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Cautions:
1. The frequency of the internal clock (I ) becomes:
2. The frequency of the peripheral clock (P ) becomes:
3. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
Rev. 5.00, 09/03, page 210 of 760
multiplication ratio of PLL circuit 1.
the frequency control register. The on/off state of PLL circuit 2 is determined by the mode.
1,
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1.
Do not set the internal clock frequency lower than the CKIO pin frequency.
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 2.
The peripheral clock frequency should not be set higher than the frequency of the CKIO
pin, higher than 33.34 MHz.
3,
2,
1/4, and
3,
4, or 6 can be used as the multiplication ratio of PLL circuit 1.
1/6 can be selected as the division ratios of dividers 1 and 2. Set the rate in
1,
1/2,

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