HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 180

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 12—I I I I R R R R L L L L S S S S Enable (IRLSEN): Enables pins IRLS3–IRLS0. This bit is valid only when the
IRQLVL bit is 1.
Bit 12: IRLSEN Description
0
1
Bits 11 and 10—IRQ5 Sense Select (IRQ51S, IRQ50S): Select whether the interrupt signal to
the IRQ5 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 11: IRQ51S Bit 10: IRQ50S Description
0
1
Bits 9 and 8—IRQ4 Sense Select (IRQ41S, IRQ40S): Select whether the interrupt signal to the
IRQ4 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 9: IRQ41S
0
1
Bits 7 and 6—IRQ3 Sense Select (IRQ31S, IRQ30S): Select whether the interrupt signal to the
IRQ3 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 7: IRQ31S
0
1
Rev. 5.00, 09/03, page 134 of 760
Pins IRLS3–IRLS0 disabled
Pins IRLS3–IRLS0 enabled
0
1
0
1
Bit 8: IRQ40S
0
1
0
1
Bit 6: IRQ30S
0
1
0
1
An interrupt request is detected at IRQ5 input falling edge
An interrupt request is detected at IRQ5 input rising edge
An interrupt request is detected at IRQ5 input low level
Reserved
Description
An interrupt request is detected at IRQ4 input falling edge
An interrupt request is detected at IRQ4 input rising edge
An interrupt request is detected at IRQ4 input low level
Reserved
Description
An interrupt request is detected at IRQ3 input falling edge
An interrupt request is detected at IRQ3 input rising edge
An interrupt request is detected at IRQ3 input low level
Reserved
(Initial value)
(Initial value)
(Initial value)
(Initial value)