HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 42

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table 8.2
Table 8.3
Table 8.4
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10 32-Bit External Device/Little-Endian Access and Data Alignment........................ 263
Table 10.11 16-Bit External Device/Little-Endian Access and Data Alignment........................ 263
Table 10.12 8-Bit External Device/Little-Endian Access and Data Alignment.......................... 264
Table 10.13 Relationship between Bus Width, AMX Bits, and Address Multiplex Output ....... 279
Table 10.14 Example of Correspondence between SH7709S and Synchronous DRAM
Table 10.15 MCSCRx Settings and MCS[x] Assertion Conditions (x: 0–7).............................. 324
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Table 11.8
Table 11.9
Table 11.10 Values in DMAC after End of Fourth Transfer ...................................................... 385
Table 11.11 Transfer Conditions and Register Settings for Transfer between External
Table 12.1
Table 12.2
Table 12.3
Table 13.1
Rev. 5.00, 09/03, page xl of xliv
Pin Configuration.................................................................................................... 183
Register Configuration............................................................................................ 183
Register States in Standby Mode ............................................................................ 188
CPG Pins and Functions ......................................................................................... 206
CPG Register .......................................................................................................... 206
Clock Operating Modes .......................................................................................... 207
Available Combinations of Clock Mode and FRQCR Values................................ 208
Register Configuration............................................................................................ 214
BSC Pins................................................................................................................. 226
BSC Registers......................................................................................................... 228
Physical Address Space Map.................................................................................. 230
Correspondence between External Pins (MD4 and MD3) and Memory Size......... 231
PCMCIA Interface Characteristics ......................................................................... 232
PCMCIA Support Interface .................................................................................... 233
32-Bit External Device/Big-Endian Access and Data Alignment .......................... 260
16-Bit External Device/Big-Endian Access and Data Alignment .......................... 261
8-Bit External Device/Big-Endian Access and Data Alignment ............................ 262
Address Pins (AMX [3:0] = 0100 (32-Bit Bus Width)).......................................... 281
DMAC Pins ............................................................................................................ 330
DMAC Registers .................................................................................................... 331
Selecting External Request Modes with RS Bits .................................................... 347
Selecting On-Chip Peripheral Module Request Modes with RS3-0 Bits................ 348
Supported DMA Transfers...................................................................................... 352
Relationship between Request Modes and Bus Modes by DMA Transfer
Category ................................................................................................................. 361
Register Configuration............................................................................................ 377
Transfer Conditions and Register Settings for Transfer between On-Chip SCI
and External Memory ............................................................................................. 383
Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Converter and External Memory ............................................................................ 384
Memory and SCIF Transmitter............................................................................... 386
TMU Pin................................................................................................................. 391
TMU Registers........................................................................................................ 391
TMU Interrupt Sources........................................................................................... 405
RTC Pins................................................................................................................. 409