HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 200

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7.2.3
Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the
break conditions of channel A. A power-on reset initializes BBRA to H'0000.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMAC Cycle Select A (CDA1, CDA0): Selects the CPU cycle or
DMAC cycle as the bus cycle of the channel A break condition.
Bit 7: CDA1
0
*
1
*: Don’t care
Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): Selects the instruction
fetch cycle or data access cycle as the bus cycle of the channel A break condition.
Bit 5: IDA1
0
1
Rev. 5.00, 09/03, page 154 of 760
Initial value:
Initial value:
Break Bus Cycle Register A (BBRA)
R/W:
R/W:
Bit:
Bit:
Bit 6: CDA0
0
1
0
Bit 4: IDA0
0
1
0
1
CDA1
R/W
15
—
R
0
7
0
CDA0
R/W
14
—
R
0
6
0
Description
Condition comparison is not performed
The break condition is the CPU cycle
The break condition is the DMAC cycle
Description
Condition comparison is not performed
The break condition is the instruction fetch cycle
The break condition is the data access cycle
The break condition is the instruction fetch cycle or data access
cycle
IDA1
R/W
13
—
R
0
5
0
IDA0
R/W
12
—
R
0
4
0
RWA1
R/W
11
—
R
0
3
0
RWA0
R/W
10
—
R
0
2
0
SZA1
R/W
—
R
9
0
1
0
(Initial value)
(Initial value)
SZA0
R/W
—
R
8
0
0
0