HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 107

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.1.4
A register that has an undefined initial value must be initialized by software. Table 3.1 shows the
configuration of the MMU control registers.
Table 3.1
Name
Page table entry register high
Page table entry register low
Translation table base register
TLB exception address register
MMU control register
Notes: 1. Initialized by a power-on reset or manual reset.
3.2
There are five registers for MMU processing. These registers are located in address space area P4
and can only be accessed from privileged mode by specifying the address.
1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which
2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to
3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the
4. The TLB exception address register (TEA) residing at address H'FFFFFFFC, which stores the
consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual
address at which the exception is generated in case of an MMU exception or address error
exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address,
but in this case the upper 22 bits of the virtual address are set. The VPN can also be modified
by software. As the ASID, software sets the number of the currently executing process. The
VPN and ASID are recorded in the TLB by the LDTLB instruction.
store the physical page number and page management information to be recorded in the TLB
by the LDTLB instruction. The contents of this register are only modified in response to a
software command. (Refer to section 3.4.3, MMU Instruction (LDTLB), and section 3.5,
MMU Exceptions.)
base address of the current page table. The hardware does not set any value in TTB
automatically. TTB is available to software for general purposes.
virtual address corresponding to a TLB or address error exception. This value remains valid
until the next exception or interrupt.
2. SV bit: undefined
Register Configuration
Register Description
Other bits: 0
Register Configuration
TTB
Abbreviation
PTEH
PTEL
TEA
MMUCR
R/W
R/W
R/W
R/W
R/W
R/W
Size
Longword
Longword
Longword
Longword
Longword
Rev. 5.00, 09/03, page 61 of 760
Initial
Value *
Undefined
Undefined
Undefined
Undefined
*
2
1
Address
H'FFFFFFF0
H'FFFFFFF4
H'FFFFFFF8
H'FFFFFFFC
H'FFFFFFE0