HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 145

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

4.5.3
1. NMI
2. IRL Interrupts
3. IRQ Pin Interrupts
4. PINT Pin Interrupts
— Conditions: NMI pin edge detection
— Operations: PC after the instruction that receives the interrupt is saved to SPC, and SR at
— Conditions: The value of the interrupt mask bits in SR is lower than the IRL3–IRL0 level
— Operations: The PC value after the instruction at which the interrupt is accepted is saved to
— Conditions: The IRQ pin is asserted, SR.IMASK is lower than the IRQ priority level, and
— Operations: The PC value after the instruction at which the interrupt is accepted is saved to
— Conditions: The PINT pin is asserted, the interrupt mask bits in SR. is lower than the PINT
— Operations: The PC value after the instruction at which the interrupt is accepted is saved to
the point the interrupt is accepted is saved to SSR. H'01C0 is set to INTEVT and
INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to PC =
VBR + H'0600. This interrupt is not masked by SR.IMASK and is accepted with top
priority when the BL bit in SR is 0. When the BL bit is 1, the interrupt is masked. See
section 6, Interrupt Controller (INTC), for more information.
and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
SPC. SR at the time the interrupt is accepted is saved to SSR. The code corresponding to
the IRL3–IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as
H'200 + [IRL3–IRL0]
RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not
set in SR.IMASK. See section 6, Interrupt Controller (INTC), for more information.
the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to
the interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to VBR + H'0600. The received level is not set in the interrupt
mask bits in SR. See section 6, Interrupt Controller (INTC), for more information.
priority level, and the BL bit in SR is 0. The interrupt is accepted at an instruction
boundary.
SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to
the interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits of SR are
set to 1 and a branch occurs to VBR + H'0600. The received level is not set in the interrupt
mask bits in SR. See section 6, Interrupt Controller (INTC), for more information.
Interrupts
H'20. See table 6.5, for the corresponding codes. The BL, MD, and
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