HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 39

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 23.19 Burst ROM Bus Cycle (No Wait) ........................................................................ 678
Figure 23.20 Burst ROM Bus Cycle (Two Waits) .................................................................... 679
Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ...................................... 680
Figure 23.22 Synchronous DRAM Read Bus Cycle (RCD
Figure 23.23 Synchronous DRAM Read Bus Cycle (RCD
Figure 23.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read
Figure 23.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read
Figure 23.26 Synchronous DRAM Write Bus Cycle (RCD
Figure 23.27 Synchronous DRAM Write Bus Cycle (RCD
Figure 23.28 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write
Figure 23.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write
Figure 23.30 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row
Figure 23.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row
Figure 23.32 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row
Figure 23.33 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row
Figure 23.34 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row
Figure 23.35 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row
Figure 23.36 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row
Figure 23.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ..................... 696
Figure 23.38 Synchronous DRAM Self-Refresh Cycle (TRAS
Figure 23.39 Synchronous DRAM Mode Register Write Cycle ............................................... 698
Figure 23.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ............................. 699
Figure 23.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
Figure 23.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait).......... 701
Figure 23.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits,
Figure 23.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)...................................... 703
Figure 23.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
Figure 23.46 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing,
RCD
RCD
RCD
RCD
Address, CAS Latency = 1).................................................................................. 689
Address, CAS Latency = 2).................................................................................. 690
Address, TPC = 0, RCD = 0, CAS Latency = 1) .................................................. 691
Address, TPC = 1, RCD = 0, CAS Latency = 1) .................................................. 692
Address) ............................................................................................................... 693
Address, TPC = 0, RCD = 0) ............................................................................... 694
Address, TPC = 1, RCD = 1) ............................................................................... 695
WAITSEL = 1)..................................................................................................... 700
Burst Pitch = 3, WAITSEL = 1)........................................................................... 702
WAITSEL = 1)..................................................................................................... 704
WAITSEL = 1)..................................................................................................... 705
0, CAS Latency
1, CAS Latency
0, TPC
1, TPC
1, TRWL = 0) ........................................................................... 687
0, TRWL = 0) ........................................................................... 688
1, TPC 1) ................................................................. 683
3, TPC 0) ................................................................. 684
0, CAS Latency
2, CAS Latency
0, TPC
2, TPC
Rev. 5.00, 09/03, page xxxvii of xliv
1, TPC
0, TRWL = 0)............ 685
1, TRWL = 1)............ 686
1) ......................... 697
1, TPC
2, TPC
4),
4),
4),
4),
0) .. 681
1) .. 682