HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 373

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11.1
The SH7709S includes a four-channel direct memory access controller (DMAC). The DMAC can
be used in place of the CPU to perform high-speed transfers between external devices that have
DACK (transfer request acknowledge signal), external memory, memory-mapped external
devices, and on-chip peripheral modules (IrDA, SCIF, A/D converter, and D/A converter). Using
the DMAC reduces the burden on the CPU and increases overall operating efficiency.
11.1.1
The DMAC has the following features.
Four channels
4-GB address space in the architecture
16-byte transfer (In 16-byte transfer, four 32-bit reads are executed, followed by four 32-bit
writes.)
Choice of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length
16 Mbytes (16,777,216 transfers)
Address mode: Dual address mode and single address mode are supported. In addition, direct
address transfer mode or indirect address transfer mode can be selected.
Channel functions: The transfer mode that can be specified depends on the channel:
Section 11 Direct Memory Access Controller (DMAC)
Dual address mode transfer: Both the transfer source and transfer destination are accessed
by address. Dual address mode has direct address transfer mode and indirect address
transfer mode.
Direct address transfer mode: The values specified in the DMAC registers indicates the
transfer source and transfer destination. Two bus cycles are required for one data transfer.
Indirect address transfer mode: Data is transferred with the address stored prior to the
address specified in the transfer source address in the DMAC. Other operations are the
same as those of direct address transfer mode. This function is only available in channel 3.
Four bus cycles are required for one data transfer.
Single address mode transfer: Either the transfer source or transfer destination peripheral
device is accessed (selected) by means of the DACK signal, and the other device is
accessed by address. One transfer unit of data is transferred in one bus cycle.
Channel 0: External request can be accepted.
Channel 1: External request can be accepted.
Channel 2: This channel has a source address reload function, which reloads a source
address every four transfers.
Overview
Features
Rev. 5.00, 09/03, page 327 of 760