HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 249

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

9.1
The on-chip oscillation circuits consist of a clock pulse generator (CPG) block and a watchdog
timer (WDT) block. The WDT is a single-channel timer that counts the clock settling time and is
used when clearing standby mode and temporary standbys, such as frequency changes. It can also
be used as an ordinary watchdog timer or interval timer.
9.1.1
The CPG has the following features:
The WDT has the following features:
Four clock modes: Selection of four clock modes for different frequency ranges, power
consumption, direct crystal input, and external clock input.
Three clocks generated independently: An internal clock for the CPU, cache, and TLB (I ); a
peripheral clock (P ) for the on-chip peripheral modules; and a bus clock (CKIO) for the
external bus interface.
Frequency change function: Internal and peripheral clock frequencies can be changed
independently using the PLL circuit and divider circuit within the CPG. Frequencies are
changed by software using frequency control register (FRQCR) settings.
Power-down mode control: The clock can be stopped for sleep mode and standby mode and
specific modules can be stopped using the module standby function.
Can be used to ensure the clock settling time: Use the WDT to cancel standby mode and the
temporary standbys which occur when the clock frequency is changed.
Can switch between watchdog timer mode and interval timer mode.
Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow.
Selection of power-on reset or manual reset.
Generates interrupts in interval timer mode: Internal timer interrupts occur after counter
overflow.
Selection of eight counter input clocks. Eight clocks ( 1 to 1/4096) can be obtained by
dividing the peripheral clock.
Overview
Features
Section 9 On-Chip Oscillation Circuits
Rev. 5.00, 09/03, page 203 of 760