MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 954

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Development Support
23.6.1
Table 23-15
and write accesses, respectively.
23-40
MSR[PR]
0
0
0
1
Register Protection
and
Table 23-16
SPR Number
Table 23-15. Development Support Registers Read Access Protection
Table 23-14. Development Support Programming Model (continued)
(Decimal)
Debug Mode
154
155
156
157
158
159
630
Enable
X
0
1
1
summarize protection features of development support registers during read
Comparator G Value Register (CMPG)
See
Comparator H Value Register (CMPH)
See
L-Bus Support Control Register 1 (LCTRL1)
See
L-Bus Support Control Register 2 (LCTRL2)
See
I-Bus Support Control Register (ICTRL)
See
Breakpoint Address Register (BAR)
See
Development Port Data Register (DPDR)
See
bit descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
In Debug Mode
Section 23.6.13, “Development Port Data Register
Table 23-23
Table 23-23
Table 23-24
Table 23-25
Table 23-26
Table 23-28
X
X
0
1
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Read is performed.
ECR is cleared when read.
Reading DPDR yields indeterminate data.
Read is performed.
ECR is not cleared when read.
Reading DPDR yields indeterminate data.
Read is performed.
ECR is cleared when read.
Program exception is generated.
Read is not performed.
ECR is not cleared when read.
Name
Result
(DPDR)” for
Freescale Semiconductor