MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 17

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.3
14.3.1
14.3.1.1
14.3.1.2
14.3.1.3
14.3.1.4
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
14.3.9
14.3.10
14.3.10.1
14.3.11
14.3.11.1
14.3.12
14.3.13
14.3.14
14.3.15
14.3.16
14.3.17
14.3.18
14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.4.1
Freescale Semiconductor
Paragraph
Number
QADC64E Block Diagram ........................................................................................... 14-1
Key Features and Quick Reference Diagrams .............................................................. 14-2
Programming the QADC64E Registers ........................................................................ 14-7
Digital Subsystem ....................................................................................................... 14-38
Features of the QADC64E Enhanced Mode Operation ............................................ 14-2
Memory Map ............................................................................................................ 14-3
Legacy and Enhanced Modes of Operation .............................................................. 14-4
Using the Queue and Result Word Table ................................................................. 14-5
External Multiplexing ............................................................................................... 14-5
QADC64E Interrupt Register ................................................................................. 14-11
Port Data Register ................................................................................................... 14-12
Port Data Direction Register ................................................................................... 14-13
Control Register 0 ................................................................................................... 14-14
Control Register 1 ................................................................................................... 14-16
Control Register 2 ................................................................................................... 14-18
Status Registers (QASR0 and QASR1) .................................................................. 14-22
Conversion Command Word Table ........................................................................ 14-28
Result Word Table .................................................................................................. 14-34
Analog-to-Digital Converter Operation .................................................................. 14-36
Channel Decode and Multiplexer ........................................................................... 14-37
Sample Buffer Amplifier ........................................................................................ 14-37
Digital to Analog Converter (DAC) Array ............................................................. 14-37
Comparator ............................................................................................................. 14-38
Bias ......................................................................................................................... 14-38
Successive Approximation Register ...................................................................... 14-38
State Machine ......................................................................................................... 14-38
Queue Priority ......................................................................................................... 14-39
Sub-Queues That are Paused .................................................................................. 14-39
Boundary Conditions .............................................................................................. 14-41
Scan Modes ............................................................................................................. 14-42
QADC64E Module Configuration Register ........................................................... 14-8
Low Power Stop Mode ......................................................................................... 14-8
Freeze Mode ......................................................................................................... 14-9
Switching Between Legacy and Enhanced Modes of Operation .......................... 14-9
Supervisor/Unrestricted Address Space ............................................................. 14-10
Analog Subsystem .............................................................................................. 14-36
Conversion Cycle Times ..................................................................................... 14-36
Disabled Mode .................................................................................................... 14-42
QADC64E Enhanced Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Chapter 14
Title
Number
Page
xvii