MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 856
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Dual-Port TPU3 RAM (DPTRAM)
20.2
20.3
The DPTRAM module consists of two separately addressable sections. The first is a set of
memory-mapped control and status registers used for configuration (DPTMCR, RAMBAR, MISRH,
MISRL, MISCNT) and testing (DPTTCR) of the DPTRAM array. The second section is the array itself.
All DPTRAM module control and status registers are located in supervisor data space. User read or write
attempts will result in a bus error.
When the TPU3 is using the RAM array for microcode control storage, none of these control registers has
any effect on the operation of the RAM array.
All addresses within the 64-byte control block will respond when accessed properly. Unimplemented
addresses will return zeros for read accesses. Likewise, unimplemented bits within registers will return
zero when read and will not be affected by write operations.
Table 20-1
internal system base address (see
Figure 1-3
20-2
•
•
•
•
— The DPTRAM array acts as a microcode storage for the TPU3 module. This provides a means
Includes built in check logic which scans the array contents and calculates the DPTRAM signature
IMB3 bus interface
Two TPU3 interface units
Byte, half-word, or word accessible
DPTRAM Configuration Block Diagram
Programming Model
to locate the DPTRAM control block in the MPC561/MPC563 address map.
of executing TPU3 code out of DPTRAM instead of TPU3 ROM.
shows the DPTRAM control and status registers. The addresses shown are offsets from the
RAM Mode
DPTRAM
MPC561/MPC563 Reference Manual, Rev. 1.2
TPU3
TPU3
Section 6.2.2.1.2, “Internal Memory Map Register
Figure 20-1. DPTRAM Configuration
TPU3 Emulation Mode
DPTRAM
TPU3
TPU3
Local Bus
Local Bus
Freescale Semiconductor
(IMMR)”). Refer to
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