MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 225
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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4.6.2
4.6.2.1
Freescale Semiconductor
1
2
,
HRESET
HRESET
MPC562/MPC564 only.
The reset value is a reset configuration word value extracted from the internal bus line. Refer to
Configuration Word
Bits
8:17
Field R
Field
Addr
3:7
18
0
1
2
MSB
16
BBC Register Descriptions
0
—
BBC Module Configuration Register (BBCMCR)
000
17
D
1
Name
TEST
BE ETRE EIR
BE
18
S
—
2
R
D
S
(RCW).”
1
ID19
Figure 4-7. BBC Module Configuration Register (BBCMCR)
19
3
2
Read Only. Any attempt to write to the DECRAM array while R is set is terminated with
an error. This causes a machine check exception for RCPU.
0 DECRAM array is Readable and Writable.
1 DECRAM array is Read only.
Data Only. The DECRAM array may be used for Instructions and Data or for Data
storage only. Any attempt to load instructions from the DECRAM array, while D is set, is
terminated with an error This causes a machine check exception for the RCPU.
0 DECRAM array holds Data and/or Instruction.
1 DECRAM array holds Data only.
Supervisor Only.
When the bit is set (S = 1), only a Supervisor program may access the DECRAM. If a
Supervisor program is accessing the array, normal read/write operation will occur. If a
User program is attempting to access the array, the access will be terminated with an
error This causes a machine check exception for the RCPU.
If S = 0, the RAM array is placed in Unrestricted Space and access by both Supervisor
and User programs is allowed.
These bits can be set in Factory test mode only. The User should treat these bits as
reserved and always write as zeros.
Reserved
Burst Enable
0 Burst access is disabled.
1 Burst access is enabled.
20
4
0
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 4-4. BBCMCR Field Descriptions
COMP
ID21
EN_
21
5
2
1
EXC_COMP
TEST
ID22
22
6
0000_0000_0000_0000
2
1
SPR 560
DECOMP_SC_
ID21
EN
23
7
Description
1
2
OERC[0:1] BTEE
ID(24:25)
24
8
25
9
2
Burst Buffer Controller 2 Module
10
26
Section 7.5.2, “Hard Reset
—
11 12 13
27 28 29
00_0000
—
DCAE TST
14
30
LSB
15
31
4-19
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