MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 937

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

23.3.1.1
For protection purposes two possible working modes are defined: debug mode enable and debug mode
disable. These working modes are selected only during reset. See
Debug mode is enabled by asserting DSCK during reset.
Freescale Semiconductor
rfi
Debug Mode Enable
0
. . .
Debug Enable Register
(DER)
.
Debug Mode Enable vs. Debug Mode Disable
. . .
.
. . .
Reset
.
. . .
Set
.
32
MPC561/MPC563 Reference Manual, Rev. 1.2
Q
Figure 23-6. Debug Mode Logic
0
. . .
. . .
Exception Cause Register
(ECR)
.
.
. . .
. . .
Decoder
.
.
. . .
. . .
Internal Debug Mode Signal
.
.
. . .
. . .
.
.
32
Figure 23-7
5
Event valid
Event
for BDM mode selection.
Freeze
ECR_OR
Development Support
23-23