MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 172

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Central Processing Unit
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. The
PowerPC ISA architecture uses instructions that are four bytes long and word-aligned. It provides for byte,
half-word, and word operand loads and stores between memory and a set of 32 GPRs.
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register,
modified, and then written back to the target location with distinct instructions.
PowerPC ISA-compliant processors follow the program flow when they are in the normal execution state.
However, the flow of instructions can be interrupted directly by the execution of an instruction or by an
asynchronous event. Either kind of exception may cause one of several components of the system software
to be invoked.
3.10.1
Table 3-17
description of the instruction set.
3-28
add (add. addo addo.)
addc (addc. addco addco.)
adde (adde. addeo addeo.)
addi
addic
addic.
addis
addme (addme. addmeo addmeo.)
addze (addze. addzeo addzeo.)
and (and.)
andc (andc.)
andi.
andis.
b (ba bl bla)
— Synchronize
— Instruction synchronize
provides a summary of RCPU instructions. Refer to the RCPU Reference Manual for a detailed
Instruction Set Summary
This grouping of the instructions does not indicate which execution unit
executes a particular instruction or group of instructions.
Mnemonic
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-17. Instruction Set Summary
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,SIMM
rD,rA,SIMM
rD,rA,SIMM
rD,rA,SIMM
rD,rA
rD,rA
rA,rS,rB
rA,rS,rB
rA,rS,UIMM
rA,rS,UIMM
target_addr
Operand Syntax
NOTE
Add
Add Carrying
Add Extended
Add Immediate
Add Immediate Carrying
Add Immediate Carrying and Record
Add Immediate Shifted
Add to Minus One Extended
Add to Zero Extended
AND
AND with Complement
AND Immediate
AND Immediate Shifted
Branch
Name
Freescale Semiconductor