MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 413
![IC MPU 32BIT W/CODE COMP 388PBGA](/photos/39/70/397084/bga-388_sml.jpg)
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Figure 10-12
note the following points:
Freescale Semiconductor
•
•
•
•
Total cycle length = 5, is determined as follows:
— Two clocks for basic cycle
— SCY = 1 determines 1 wait state, which is multiplied by two due to TRLX being set (2 + (SCY
— Extra clock is added due to TRLX effect on the strobes.
Because TRLX is set, assertion of the CS and WE strobes is delayed by one clock cycle.
CS assertion is delayed an additional one quarter clock cycle because ACS = 10.
The total cycle length = three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— An extra clock cycle is required due to the effect of TRLX on the strobes.
Address
x 2)).
CLOCK
RD/WR
WE/BE
through
Data
Figure 10-11. Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1)
OE
CS
TS
TA
Figure 10-14
MPC561/MPC563 Reference Manual, Rev. 1.2
are examples of write accesses using relaxed timing. In
ACS = ‘00’ & TRLX = ‘1’
ACS = ‘11’ & TRLX = ‘1’
WEBS = ‘1’,Line Acts as BE
in Read.
Memory Controller
Figure
10-12,
10-15
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