MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 767

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

17.9.3.5.2
The single output compare operation is selected by writing to only one of the two data registers (A or B),
thus enabling only one of the comparators. Following the first successful match on the enabled channel,
the output level is fixed and remains at the same level indefinitely with no further software intervention
being required. To generate a single output compare, the OCAB mode should be used to generate a flag on
both the A and the B match.
Figure 17-20
Freescale Semiconductor
Output signal
Mode selection; MODE0 = 0
Counter Bus
Internal Register, not accessible to software
16-bit
Register B1
Register B2
Register A
FLAG bit
provides an example of how the MDASM can be used to perform a single output compare.
Write to A and B
Single Output Compare Operation
In this mode, registers A and B2 are accessible to the user software (at
consecutive addresses).
0x0500
0x1000
0xxxxx
0x1100
Figure 17-19. Single Shot Output Pulse Example
MPC561/MPC563 Reference Manual, Rev. 1.2
A Event
0x1000
0xxxxx
0x1100
0x1000
0x1000
B Event
0xxxxx
0x1100
0x1100
NOTE
FLAG reset
by software
0x1000
0xxxxx
0x1100
0x0000
Reoccurrences of the timer count do not
A and B have been written again.
trigger the output pulse unless r egisters
Modular Input/Output Subsystem (MIOS14)
0x1000
0xxxxx
0x1100
0x1000
0x1000
0xxxxx
0x1100
0x1100
17-35