MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1049

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

24.14.2.4 RCPU Development Access Flow Diagram
Figure 24-83
signals.
Freescale Semiconductor
DEBUG MODE NOT ENALBED
*(exit loop via READI reset (*A*)
or system reset (*B*))
(synch.self-clk mode)
Device sends DSDO Message
Tool sends DSDI Message
*A*
*B*
has flow diagram describing how the RCPU development access can be achieved via READI
(@ subsequent READI reset)
DSDI=1
(@ subsequent RCPU reset)
(DME=0)
Figure 24-83. RCPU Development Access Flow Diagram
DSCK=0 within 8 clocks of SRESET
(Debug Mode not enabled) No
negation to NOT enter debug mode
DSDI=1 (sync. self-clk mode)
MPC561/MPC563 Reference Manual, Rev. 1.2
(No Debug out-of-reset) No
Tools Negates HRESET 16 clocks after receiving Device Ready
Tool sends Download Request Message and configures
*(exit loop via
READI reset
(*A*) or via
system reset
(*B*))
READI module (assign DPA, DME & DOR, etc.)
(DPA, DME, DOR, etc. bits locked)
Tool Asserts and Negates RSTI
DEBUG MODE ENABLED
Device sends DID message
No
No
Entry?
BDM
Exit?
BDM
Device sends DSDO Message
Tool sends DSDI Message
Tool Asserts HRESET
DME=1
DOR=1
(DME=1)
Device sends Debug Mode Status
?
?
Yes
Yes (Debug Mode enabled)
Yes
DSCK=1 until 16 clocks after SRESET
“BDM entry” (status bit = 1)
Device sends Debug Mode
“BDM exit” (status bit = 0)
negation to enter debug mode
DSDI=1 (sync. self-clk mode)
Status Message
Yes (Debug out-of-reset)
Message
READI Module
24-81