MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 819
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
1
(a) If ENRX is disabled, no data will shift into the PPM.
(b) If ENRX is asserted while ENTX=1, the first data bit received will be the data that is transmitted from the PPM, and
2
(a) If ENTX is disabled, no data will shift out of the PPM and the PPM output signals, PPM_TX0 and PPM_TX1 will be
(b) If ENTX is asserted while ENRX = 1, the first data bits transmitted out of the PPM will be the data that was received
Enable RX.
not RX0. See
Enable TX.
high.
into the PPM. See
11:15
Bits
10
Figure
Name
CM
—
Figure
18-10. To receive the first data frame correctly, ENRX and ENTX should be set simultaneously.
Continuous Mode.
0 Non-continuous mode (default). Transmit and/or receive one data frame when STR = 1.
(STR will be automatically cleared by the PPM after the transfer of one data frame.)
1 Data will continuously be transmitted and/or received as long as Transmit and Receive
are enabled.
Refer to
Note: Ensure PPMPCR[STR]=0 when setting PPMPCR[CM]=1
Reserved
18-11. To transmit the first data frame correctly, set ENTX and ENRX simultaneously.
Table 18-3. PPMPCR Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 18-5
SAMP[0:2]
100 – 111
Table 18-4. SAMP[0:2] Bit Settings
000
001
010
011
for more information.
Description
Every 16 TCLK
Every 2 TCLK
Every 4 TCLK
Every 8 TCLK
Sample Rate
Every TCLK
Peripheral Pin Multiplexing (PPM) Module
18-13
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