MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1005

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

24.7.7.2
Refer to
non-debug mode. The only difference between non-debug mode reset configuration and debug mode reset
configuration are the values of the DOR and DME fields in the DC register.
24.7.7.3
Refer to
24.7.7.4
If EVTI is negated at negation of RSTI, the READI module will be disabled. No trace output will be
provided, and output auxiliary signals will be three-stated. This is illustrated in
24.7.7.5
Freescale Semiconductor
•
•
•
System
Clock
RSTI
EVTI
An error message is sent out when an invalid TCODE is detected by the signal input formatter.
Refer to
An error message is sent out when an invalid access opcode is detected in auxiliary input messages
by the signal input formatter. Refer to
details.
If the TCODE is valid, then READI will expect that the correct number of packets have been
received and no further checking will be performed. If the number of packets received by READI
is not correct, READI response is not defined, unless the message is a download request message
(refer to
Section 24.7.7.1, “Reset Configuration for Debug
Section 24.2.2,
Reset configuration information must be valid on EVTI
at least 4 clocks prior to RSTI negation.
Reset Configuration for Non-Debug Mode
Secure Mode
Disabled Mode
Guidelines for Transmitting Input Messages
Section 24.10.8.2, “Invalid
Section 24.6.4, “Partial Register
“Security,” for further details.
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 24-18. READI Module Disabled
EVTI is sampled at the negation of RSTI. Since EVTI is
negated, the READI module is disabled.
Message,” for further details.
Section 24.10.8.3, “Invalid Access
Updates,” for further details).
Mode,” for details on reset configuration for
Figure
Opcode,” for further
24-18.
READI Module
24-37