MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 205

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

detected and data storage interrupt is never generated by the hardware. In the RCPU, the instruction can
be partially executed only in the case of the load/store instructions that cause multiple accesses to the
memory subsystem. These instructions are:
In the last case, the store instruction can be partially completed if one of the accesses (except the first one)
causes the data storage protection error. The implementation-specific data storage protection interrupt is
taken in this case. For the update forms, the update register (rA) is not altered.
3.15.6
Descriptions of the timebase and decrementer registers can be found in
and
3.15.7
Any other OEA optional facilities and instructions (except those that are discussed here) are not
implemented by the RCPU hardware. Attempting to execute any of these instructions causes an
implementation dependent software emulation interrupt to be taken.
Freescale Semiconductor
•
•
Protection,” and in
Multiple/string instructions
Unaligned load/store instructions
Timer Facilities
Optional Facilities and Instructions
Chapter 8, “Clocks and Power
MPC561/MPC563 Reference Manual, Rev. 1.2
Control.”
Chapter 6, “System Configuration
Central Processing Unit
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