MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 347

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
Special Transfer Start
Signal Name
Burst inhibit/
Bus request
Bus grant
Bus busy
BI / STS
BG
BR
BB
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Pins
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Active
Low
Low
Low
Low
Arbitration
I/O
O
O
O
O
I
I
I
I
Burst Inhibit: Driven by the slave device to which the
current transaction was addressed. Indicates that the
current slave does not support burst mode.
Burst Inhibit: Driven by the MPC561/MPC563 when
the slave device is controlled by the on-chip Memory
Controller. The MPC561/MPC563 also asserts BI for
any external master burst access to internal
MPC561/MPC563 memory space.
Special Transfer Start: Driven by the
MPC561/MPC563 when it owns the external bus.
Indicates the start of a transaction on the external bus
or signals the beginning of an internal transaction in
show cycle mode.
When the internal arbiter is enabled, BR assertion
indicates that an external master is requesting the
bus.
Driven by the MPC561/MPC563 when the internal
arbiter is disabled and the chip is not parked.
When the internal arbiter is enabled, the
MPC561/MPC563 asserts this signal to indicate that
an external master may assume ownership of the bus
and begin a bus transaction. The BG signal should be
qualified by the master requesting the bus in order to
ensure it is the bus owner:
Qualified bus grant = BG & ~ BB
When the internal arbiter is disabled, BG is sampled
and properly qualified by the MPC561/MPC563 when
an external bus transaction is to be executed by the
chip.
When the internal arbiter is enabled, the
MPC561/MPC563 asserts this signal to indicate that it
is the current owner of the bus.
When the internal arbiter is disabled, the
MPC561/MPC563 asserts this signal after the
external arbiter has granted the ownership of the bus
to the chip and it is ready to start the transaction.
When the internal arbiter is enabled, the
MPC561/MPC563 samples this signal to get
indication of when the external master ended its bus
tenure (BB negated).
When the internal arbiter is disabled, the BB is
sampled to properly qualify the BG line when an
external bus transaction is to be executed by the chip.
Description
External Bus Interface
9-7