MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1281

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Note: All delays are in system clock periods.
Freescale Semiconductor
1
2
3
4
5
6
7
MPWMI input pin to MPWMSCR_PIN
status set
CPSM enable to output set
MPWMSM Enable to output set (MIN)
MPWMSM Enable to output set (MAX)
Interrupt Flag to output pin reset (period
start)
Minimum output resolution depends on MPWMSM and MCPSM prescaler settings.
Maximum resolution is obtained by setting CPSMPSL[3:0] =0x2 and MPWMSCR_CP[7:0] =0xFF.
Excluding the case where the output is always “0”.
With MPWMSM enabled before enabling the MCPSM. Please also see NOTE 1 on the MCPSM timing
information.
The exact timing from MPWMSM enable to the pin being set depends on the timing of the register write and the
MCPSM VS_PCLK.
When MCPSMSCR_PSL = 0x0000, this gives a prescale value of 16 and it is 16 which should be used in these
calculations. When MCPSMSCR_PSL = 0x0001, the CPSM is inactive.
The interrupt is set before the output pin is reset (Signifying the start of a new period).
MPWMO output pin
7
f
Characteristic
SYS
Figure F-48. MPWMSM Minimum Output Pulse Example Timing Diagram
f
SYS
is the internal system clock for the IMB3 bus.
Table F-24. MPWMSM Timing Characteristics (continued)
4
MPC561/MPC563 Reference Manual, Rev. 1.2
5
5
Symbol
t
t
t
t
PWMO
t
PWMP
PWME
PWME
FLGP
t
min
PIN
NOTE
(MPWMPERR - MPWMPULR + 1) *
(256 - MPWMSCR_CP) * MCPSMSCR_PSL + 1
(MPWMPERR - MPWMPULR) * (256 - MPWMSCR_CP) *
MCPSMSCR_PSL + 3 +
(255 - MPWMSCR_CP) * MCPSMSCR_PSL
t
(256 - MPWMSCR_CP) * MCPSMSCR_PSL - 1
PWME
(MIN) + MCPSMSCR_PSL - 1
Min
1
6
Electrical Characteristics
Max
2
6
6
F-65