MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1158

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

TPU3 ROM Functions
D-6
0
ADDRESS OFFSETS
0x30XX(W+1)E
1
0x30XX(W+1)0
0x30XX(W+1)2
0x30XXWC
0x30XXW0
0x30XXW2
0x30XXW4
0x30XXW6
0x30XXW8
0x30XXWA
0x30XXWE
2
0
0
0
:
3
1
1
1
0
0
= Written By RCPU
= Written By TPU
Channel Function Select
Host Sequence
Host Service Request
Channel Priority
Channel Interrupt Enable 0 – Channel Interrupt Disabled
Channel Interrupt Status
1.
NAME
0
Not available on all channels.
1
LOOP_CNT
MPC561/MPC563 Reference Manual, Rev. 1.2
REF_ADDR
2
Figure D-3. QOM Parameters
3
xxxx – QOM Function Number.
See
00 – Single-Shot Mode
01 – Loop Mode
10 – Continuous Mode
11 – Continuous Mode
00 – No Host Service (Reset Condition)
01 – Initialize, No Pin Change
10 – Initialize, Pin Low
11 – Initialize, Pin High
00 – Disabled
01 – Low Priority
10 – Medium Priority
11 – High Priority
1 – Channel Interrupt Enabled
0 – Channel Interrupt Not Asserted
1 – Channel Interrupt Asserted
Assigned during microcode assembly.
4
PARAMETER RAM
CONTROL BITS
Table D-1
= Written by RCPU and TPU
= Unused Parameters
5
OFFSET_14
OFFSET_5
OFFSET_6
OFFSET_7
OFFSET_8
6
(LAST_MATCH_TM)
OFFSET_1
OFFSET_2
OFFSET_3
OFFSET_4
B
7
OPTIONS
BITS
:
8
1
1
1
1
1
9
LAST_OFF_ADDR
10
For address offsets: XX=41 for
TPU_A, 45 for TPU_B
YY=40 for TPU_A, 44
for TPU_B
PRAM Address Offset Map.
See
11
OFF_PTR
W = Channel Number
Table 19-24
12 13 14 15
0x30YY1C – 0x30YY1E
0x30YY0C – 0x30YY12
0x30YY18 – 0x30YY1A
0x30YY14 – 0x30YY16
Freescale Semiconductor
ADDRESSES
for the
0x30YY0A
0x30YY20
A
C
:
:
:
:
:
:
:
:
:
:
Param 0
Param 1
Param 2
Param 3
Param 4
Param 5
Param 6
Param 7
Param 8
Param 9
Param 15