MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 396

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

External Bus Interface
Show cycles are activated by properly setting the SIUMCR register bits. Refer to
Module Configuration Register
in the ICTRL register. Refer to
L2U_MCR register. Refer to
In a burst show cycle only the first data beat is shown externally. Refer to
transaction encodings.
Instruction show cycle bus transactions have the following characteristics (see
The compressed address is driven on the external bus in the following manner:
See
Features” for more details about decompression mode.
9-56
•
•
•
•
•
•
Chapter 4, “Burst Buffer Controller 2
One clock cycle
Address phase only; in decompression on mode part of the compressed address is driven on data
lines together with address lines. The external bus interface adds one clock delay between a read
cycle and such show cycle.
STS assertion only (no TA assertion)
ADDR[0:29] = the word base address;
DATA[0] = operating mode:
— 0 = decompression off mode;
— 1 = decompression on mode;
DATA[1:4] = bit pointer
Table
Table
(SIUMCR).” Construction visibility is controlled by the ISCT_SER bits
MPC561/MPC563 Reference Manual, Rev. 1.2
11-7.
23-26. Data visibility is controlled by the LSHOW bits of the
Module” and
Appendix A, “MPC562/MPC564 Compression
Table 9-8
Figure
Section 6.2.2.1.1, “SIU
Freescale Semiconductor
for show cycle
9-41):