MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 373

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.7.1
The potential bus master asserts BR to request bus mastership. BR should be negated as soon as the bus is
granted, the bus is not busy, and the new master can drive the bus. If more requests are pending, the master
can keep asserting its bus request as long as needed. When configured for external central arbitration, the
MPC561/MPC563 drives this signal when it requires bus mastership. When the internal on-chip arbiter is
used, this signal is an input to the internal arbiter and should be driven by the external bus master.
9.5.7.2
The arbiter asserts BG to indicate that the bus is granted to the requesting device. This signal can be
negated following the negation of BR or kept asserted for the current master to park the bus.
When configured for external central arbitration, BG is an input signal to the MPC561/MPC563 from the
external arbiter. When the internal on-chip arbiter is used, this signal is an output from the internal arbiter
to the external bus master.
Freescale Semiconductor
1. Assert BR
1. Wait for BB to be negated.
Bus Request
Bus Grant
2. Assert BB to become next master
3. Negate BR
1. Perform data transfer
1. Negate BB
Acknowledge Bus Mastership
Release Bus Mastership
Operate as Bus Master
Requesting Device
Request the Bus
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 9-24. Bus Arbitration Flowchart
1. Negate BG (or keep asserted to park
1. Assert BG
Grant Bus arbitration
Terminate Arbitration
bus master
Arbiter
External Bus Interface
9-33