MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 265

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

6.2.2.1.1
The SIUMCR contains bits which configure various features in the SIU module. The register contents are
shown below.
Freescale Semiconductor
1
9:10
Bits
HRESET ID0
HRESET
1:3
4:7
The reset value is a reset configuration word value, extracted from the internal data bus line. Refer to
11
12
0
8
Reset Configuration Word
Field EARB
Field
Addr
DSHW
DBGC
ATWC
Name
EARB
EARP
DBPC
MSB
SIU Module Configuration Register (SIUMCR)
All SIUMCR fields which are controlled by the reset configuration word
should not be changed by software while the corresponding functions are
active.
—
16
0
0
—
1
ID[17:18]
17
1
SC
External arbitration
0 Internal arbitration is performed
1 External arbitration is assumed
External arbitration request priority. This field defines the priority of an external master’s
arbitration request. This field is valid when EARB is cleared. Refer to
Bus
Reserved
Data show cycles. This bit selects the show cycle mode to be applied to U-bus data cycles (data
cycles to IMB modules and Flash EEPROM). This field is locked by the DLK bit. Note that
instruction show cycles are programmed in the ICTRL and L-bus data show cycles are
programmed in the L2UMCR.
0 Disable show cycles for all internal data cycles
1 Show address and data of all internal data cycles
Debug pins configuration. Refer to
Reserved.
Address write type enable configuration. This bit configures the pins to function as byte write
enables or address types for debugging purposes.
0 WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]
1 WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
EARP
Figure 6-12. SIU Module Configuration Register (SIUMCR)
18
2
Arbiter,” for details.
1
(RCW).”
RCTX MLRC
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
000_0000_0
Table 6-7. SIUMCR Bit Descriptions
20
4
21
5
—
22 23
6
—
WARNING
7
DSHW
MTSC NOS
0x2F C000
24
Table
8
0_0000_0000_0000
6-8.
HOW EICEN
Description
25
9
ID[9:10]
DBGC
10
26
1
1
LPMASK
ID11
_EN
—
11
27
System Configuration and Protection
1
Section 9.5.7.4, “Internal
BURST
ATWC
ID12
_EN
12
28
1
Section 7.5.2, “Hard
13
29
GPC
000
14
30
—
DLK
LSB
15
31
6-25