MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 45

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

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Freescale Semiconductor
Figure
Number
4 Beat Burst Read with Short Setup Time (Zero Wait State) ............................................... 10-10
GPCM–Memory Devices Interface ...................................................................................... 10-12
Memory Devices Interface Basic Timing (ACS = 00, TRLX = 0)....................................... 10-13
Peripheral Devices Interface ................................................................................................. 10-13
Peripheral Devices Basic Timing (ACS = 11, TRLX = 0) ................................................... 10-14
Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1).................................... 10-15
Relaxed Timing — Write Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1) ................ 10-16
Relaxed Timing — Write Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1) ................ 10-17
Relaxed Timing — Write Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1.................. 10-18
Consecutive Accesses (Write After Read, EHTR = 0) ......................................................... 10-19
Consecutive Accesses (Write After Read, EHTR = 1) ......................................................... 10-20
Consecutive Accesses
(Read After Read From Different Banks, EHTR = 1) .......................................................... 10-21
Consecutive Accesses (Read After Read from Same Bank, EHTR = 1).............................. 10-22
Aliasing Phenomenon Illustration ........................................................................................ 10-26
Synchronous External Master
Configuration for GPCM-Handled Memory Devices .......................................................... 10-29
Synchronous External Master Basic Access (GPCM Controlled)........................................ 10-30
Memory Controller Status Register (MSTAT) ..................................................................... 10-32
Memory Controller Base Registers 0–3 (BR0–BR3) ........................................................... 10-32
Memory Controller Option Registers 1–3 (OR0–OR3) ....................................................... 10-34
Dual-Mapping Base Register (DMBR) ................................................................................ 10-36
Dual-Mapping Option Register (DMOR)............................................................................. 10-37
L2U Bus Interface Block Diagram ......................................................................................... 11-3
DMPU Basic Functional Diagram .......................................................................................... 11-5
Region Base Address Example............................................................................................... 11-7
L2U Module Configuration Register (L2U_MCR) .............................................................. 11-14
L2U Region x Base Address Register (L2U_RBAx) ........................................................... 11-14
L2U Region X Attribute Register (L2U_RAx) .................................................................... 11-15
L2U Global Region Attribute Register (L2U_GRA) ........................................................... 11-16
UIMB Interface Module Block Diagram................................................................................ 12-2
IMB3 Clock – Full-Speed IMB3 Bus ..................................................................................... 12-3
IMB3 Clock – Half-Speed IMB3 Bus .................................................................................... 12-3
Interrupt Synchronizer Signal Flow........................................................................................ 12-4
Time-Multiplexing Protocol for IRQ Signals ......................................................................... 12-5
Interrupt Synchronizer Block Diagram................................................................................... 12-6
UIMB Module Configuration Register (UMCR) ................................................................... 12-7
Pending Interrupt Request Register (UIPEND)...................................................................... 12-9
QADC64E Block Diagram ..................................................................................................... 13-1
QADC64E Conversion Queue Operation............................................................................... 13-5
MPC561/MPC563 Reference Manual, Rev. 1.2
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