LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 965

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.2.6.4 Event set enable register
Table 908. Interrupt clear enable register (CLR_EN - address 0x4004 4FD8) bit description
Table 909. Event set enable register (SET_EN - address 0x4004 4FDC) bit description
Bit
13
14
15
16
18:17 -
19
31:20 -
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Symbol
TIM2_CLREN
TIM6_CLREN
QEI_CLREN
TIM14_CLREN
RESET_CLREN
Symbol
WAKEUP0_SETEN
WAKEUP1_SETEN
WAKEUP2_SETEN
WAKEUP3_SETEN
ATIMER_SETEN
RTC_SETEN
BOD_SETEN
WWDT_SETEN
ETH_SETEN
USB0_SETEN
USB1_SETEN
-
CAN_SETEN
TIM2_SETEN
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Writing a 1 to this bit clears the event enable bit 13 in the
ENABLE register.
Writing a 1 to this bit clears the event enable bit 14 in the
ENABLE register.
Writing a 1 to this bit clears the event enable bit 15 in the
ENABLE register.
Writing a 1 to this bit clears the event enable bit 16 in the
ENABLE register.
Reserved.
Writing a 1 to this bit clears the event enable bit 19 in the
ENABLE register.
Reserved.
Description
Writing a 1 to this bit sets the event enable bit 0 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 1 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 2 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 3 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 4 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 5 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 6 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 7 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 8 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 9 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 10 in the
ENABLE register.
Reserved.
Writing a 1 to this bit sets the event enable bit 12 in the
ENABLE register.
Writing a 1 to this bit sets the event enable bit 13 in the
ENABLE register.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reset
value
-
-
-
-
-
-
-