LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 270

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
16.6.5 DMA Interrupt Error Clear Register
16.6.6 DMA Raw Interrupt Terminal Count Status Register
Table 200. DMA Interrupt Error Status Register (INTERRSTAT, address 0x4000 200C) bit
The INTERRCLR Register is write-only and clears the error interrupt requests. When
writing to this register, each data bit that is HIGH causes the corresponding bit in the
status register to be cleared. Data bits that are LOW have no effect on the corresponding
bit in the register.
Table 201. DMA Interrupt Error Clear Register (INTERRCLR, address 0x4000 2010) bit
The RAWINTTCSTAT Register is read-only and indicates which DMA channel is
requesting a transfer complete (terminal count interrupt) prior to masking. (Note: the
IntTCStat Register contains the same information after masking.) A HIGH bit indicates
that the terminal count interrupt request is active prior to masking.
Table 202. DMA Raw Interrupt Terminal Count Status Register (RAWINTTCSTAT, address
Bit
7:0
31:8
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
INTERRCLR
-
Symbol
INTERRSTAT Interrupt error status for DMA channels. Each bit
-
Symbol
RAWINTTCSTAT Status of the terminal count interrupt for DMA
-
description
description
0x4000 2014) bit description
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Description
Writing a 1 clears the error interrupt request (IntErrStat)
for DMA channels. Each bit represents one channel:
0 - writing 0 has no effect.
1 - clears the corresponding channel error interrupt.
Reserved. Read undefined. Write reserved bits as zero. -
Description
represents one channel:
0 - the corresponding channel has no active error
interrupt request.
1 - the corresponding channel does have an active
error interrupt request.
Reserved. Read undefined.
Rev. 00.13 — 20 July 2011
Description
channels prior to masking. Each bit represents one
channel:
0 - the corresponding channel has no active
terminal count interrupt request.
1 - the corresponding channel does have an active
terminal count interrupt request.
Reserved. Read undefined.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x00
Reset
value
0x00
-
Reset
value
0x00
-
270 of 1164
Access
WO
-
-
Access
RO
-
Access
RO