LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 274

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
16.6.14 DMA Synchronization Register
16.6.15 DMA Channel registers
16.6.16 DMA Channel Source Address Registers
Table 209. DMA Configuration Register (CONFIG, address 0x4000 2030) bit description
The Sync Register is read/write and enables or disables synchronization logic for the
DMA request signals. The DMA request signals consist of the BREQ[15:0], SREQ[15:0],
LBREQ[15:0], and LSREQ[15:0]. A bit set to 0 enables the synchronization logic for a
particular group of DMA requests. A bit set to 1 disables the synchronization logic for a
particular group of DMA requests. This register is reset to 0, synchronization logic
enabled.
Table 210. DMA Synchronization Register (SYNC, address 0x4000 2034) bit description
The channel registers are used to program the eight DMA channels. These registers
consist of:
When performing scatter/gather DMA, the first four of these are automatically updated.
The eight read/write CSRCADDR Registers (C0SRCADDR to C7SRCADDR) contain the
current source address (byte-aligned) of the data to be transferred. Each register is
programmed directly by software before the appropriate channel is enabled. When the
DMA channel is enabled this register is updated:
Bit
2
31:3 -
Bit
15:0
31:16
•
•
•
•
•
Eight CSRCADDR Registers.
Eight CDESTADDR Registers.
Eight CLLI Registers.
Eight CCONTROL Registers.
Eight CCONFIG Registers.
Symbol Value
M1
Symbol
DMACSYNC Controls the synchronization logic for DMA request
-
0
1
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Description
AHB Master 1 endianness configuration:
Little-endian mode (default).
Big-endian mode.
Reserved. Read undefined. Write reserved bits as
zero.
Description
signals. Each bit represents one set of DMA request
lines as described in the preceding text:
0 - synchronization logic for the corresponding DMA
request signals are disabled.
1 - synchronization logic for the corresponding
request line signals are enabled.
Reserved. Read undefined. Write reserved bits as
zero.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x00
Reset
value
0x00
-
274 of 1164
Access
R/W
Access
R/W
-