LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 651

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.7.9.3 MCPWM Interrupt Enable clear address
Table 563. MCPWM interrupt enable set register (INTEN_SET - address 0x400A 0054) bit
Writing ones to this write-only address clears the corresponding bits in INTEN, thus
disabling interrupts.
Table 564. PWM interrupt enable clear register (INTEN_CLR - address 0x400A 0058) bit
Bit
7
9
10
11
14:12 -
15
31:16 -
Bit
0
1
2
3
4
5
6
7
8
9
10
14:11 -
15
31:16 -
Symbol
-
ILIM2_SET
IMAT2_SET
ICAP2_SET
ABORT_SET Writing a one sets the corresponding bit in INTEN, thus enabling
Symbol
ILIM0_CLR
IMAT0_CLR
ICAP0_CLR
-
ILIM1_CLR
IMAT1_CLR
ICAP1_CLR
-
ILIM2_CLR
IMAT2_CLR
ICAP2_CLR
ABORT_CLR Writing a one clears the corresponding bit in INTEN, thus disabling
description
description
All information provided in this document is subject to legal disclaimers.
Description
Reserved.
Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.
Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.
Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.
Reserved.
the interrupt.
Reserved.
Description
Writing a one clears the corresponding bit in INTEN, thus disabling
the interrupt.
Writing a one clears the corresponding bit in INTEN, thus disabling
the interrupt.
Writing a one clears the corresponding bit in INTEN, thus disabling
the interrupt.
Reserved.
Writing a one clears the corresponding bit in INTEN, thus disabling
the interrupt.
Writing a one clears the corresponding bit in INTEN, thus disabling
the interrupt.
Writing a one clears the corresponding bit in INTEN, thus disabling
the interrupt.
Reserved.
Writing a one clears the corresponding bit in INTEN, thus disabling
the interrupt.
Writing a one clears the corresponding bit in INTEN, thus disabling
the interrupt.
Writing a one clears the corresponding bit in INTEN, thus disabling
the interrupt.
Reserved.
the interrupt.
Reserved.
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
651 of 1164
Reset
value
-
-
-
-
-
-
-
Reset
value
-
-
-
-
-
-
-
-
-
-
-
-
-
-