LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 535

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 443. Receive descriptor fields 0 (RDES0)
Bit
0
1
2
3
4
5
6
7
8
9
Symbol
ESA
CE
DE
RE
RWT
FT
LC
TSA
LS
FS
All information provided in this document is subject to legal disclaimers.
Description
Extended Status Available/Rx MAC Address
When either Advanced Timestamp or IP Checksum Offload (Type 2) is
present, this bit, when set, indicates that the extended status is available in
descriptor word 4 (RDES4). This is valid only when the Last Descriptor bit
(RDES0[8]) is set. When Advance Timestamp Feature or IPC Full Offload is
not selected, this bit indicates Rx MAC Address status. When set, this bit
indicates that the Rx MAC Address registers value (1 to 31) matched the
frame’s DA field. When reset, this bit indicates that the Rx MAC Address
Register 0 value matched the DA field.
CRC Error
When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error
occurred on the received frame. This field is valid only when the Last
Descriptor (RDES0[8]) is set.
Dribble Bit Error
When set, this bit indicates that the received frame has a non-integer multiple
of bytes (odd nibbles). This bit is valid only in MII Mode.
Receive Error
When set, this bit indicates that the gmii_rxer_i signal is asserted while
gmii_rxdv_i is asserted during frame reception. This error also includes carrier
extension error in MII and Half-duplex mode. Error can be of less/no
extension, or error (rxd  0f) during extension.
Receive Watchdog Timeout
When set, this bit indicates that the Receive Watchdog Timer has expired
while receiving the current frame and the current frame is truncated after the
Watchdog Timeout.
Frame Type
When set, this bit indicates that the Receive Frame is an Ethernet-type frame
(the LT field is greater than or equal to 0x0600). When this bit is reset, it
indicates that the received frame is an IEEE802.3 frame. This bit is not valid
for Runt frames less than 14 bytes.
Late Collision
When set, this bit indicates that a late collision has occurred while receiving
the frame in Half-Duplex mode.
Timestamp Available/IP Checksum Error (Type1) /Giant Frame
When Advanced Timestamp feature is present, when set, this bit indicates that
a snapshot of the Timestamp is written in descriptor words 6 (RDES6) and 7
(RDES7). This is valid only when the Last Descriptor bit (RDES0[8]) is set.
When IP Checksum Engine (Type 1) is selected, this bit, when set, indicates
that the 16-bit IPv4 Header checksum calculated by the core did not match the
received checksum bytes. Otherwise, this bit, when set, indicates the Giant
Frame Status. Giant frames are larger-than-1,518-byte (or 1,522-byte for
VLAN) normal frames and larger-than-9,018-byte (9,022-byte for VLAN) frame
when Jumbo Frame processing is enabled.
Last Descriptor
When set, this bit indicates that the buffers pointed to by this descriptor are the
last buffers of the frame
First Descriptor
When set, this bit indicates that this descriptor contains the first buffer of the
frame. If the size of the first buffer is 0, the second buffer contains the
beginning of the frame. If the size of the second buffer is also 0, the next
Descriptor contains the beginning of the frame.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
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